Senior RTL Engineer, Interconnect Design

Compensation

$225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
• 401(k) retirement plan with employer match
• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
• Mental health and wellness support
• Employer-paid basic life and disability coverage
• Annual learning and development stipend to fuel your professional growth
• Daily meals in our offices, and meal delivery credits as eligible
• Relocation support for eligible employees
• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is building next-generation AI-native silicon and infrastructure to support large-scale training and inference systems.

Within Hardware, the SoC design team works across architecture, RTL design, verification, physical design, performance, firmware, and systems engineering to deliver production-quality silicon for OpenAI’s supercomputing infrastructure.

About the Role

We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale.

This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution.

Responsibilities

• Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces.
• Drive third-party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and design integrity, leveraging deep technical and non-technical leadership skills.
• Perform substantial direct microarchitecture and RTL coding work.
• Collaborate with architecture and design team members on the overall solution and execution plan for cutting-edge large-scale custom silicon.
• Work with performance and architecture teams to analyze traffic patterns, identify bottlenecks, and optimize interconnect behavior under realistic system workloads.
• Collaborate with design verification teams to develop verification strategies, coverage plans, assertions, stress scenarios, and debug approaches for highly concurrent fabric behavior.
• Partner with physical design teams to ensure interconnect structures are implementable at target frequency, power, and area, including floorplan-aware design, pipeline strategy, timing closure, and congestion management.
• Provide technical leadership through design reviews, architecture reviews, documentation, mentoring, and development of reusable RTL and integration methodologies.
• Leverage experience to help raise the bar on design work inside our team.
• Roll up your sleeves and get your hands dirty!

Requirements

• Extensive industry experience designing and delivering complex SoC interconnect, NoC, coherent fabric, memory subsystem, cache-coherent, or chip-level integration solutions.
• A strong track record of owning major RTL blocks or SoC subsystems from microarchitecture through tape-out and silicon bring-up.
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• Strong understanding of interconnect concepts such as topology, routing, arbitration, virtual channels, flow control, buffering, ordering, quality of service, coherency, deadlock avoidance, congestion management, and performance monitoring.
• Experience with common on-chip or chip-to-chip protocols and interfaces, such as AXI, APB, CXL, PCIe, Ethernet.
• Experience building custom networking protocols or protocol extensions.
• Experience working designing and implementing subsystems in the context of large-scale systems built with RDMA/RoCE or other HPC-style system-level interconnects.
• Familiarity and deep experience with the full spectrum of industry-standard RTL-adjacent development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test considerations.
• Experience working closely with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.
• Strong judgment in making practical design tradeoffs across performance, power, area, schedule, verification risk, and physical implementation constraints.
• Excellent communication skills and the ability to provide technical direction, mentor engineers, and drive alignment across multiple teams.
• Passion for achieving high leverage through complexity reduction, automation, and creative pragmatism.