We're looking for a Senior IC Packaging Design Engineer to join our package team and focus on delivering and designing state-of-the-art high-speed Interconnect systems for Supercomputers and Datacenters.
As part of our IC Packaging design team, you will collaborate to implement high-speed and PDN design for ASIC packages. You will develop symbols, pad stacks, and perform substrate package routing, placement, stack-up, reference plane, and power distribution using Cadence APD (Allegro) or SiP tools.
Key responsibilities include:
- Optimizing package pin-out incorporating system-level trade-offs of pins assignment
- Developing methodologies to improve layout environment, productivity, reliability, and schedule considerations
- Collaborating closely with SI/PI/HW design teams and product teams
- Planning, ensuring stakeholder management, and leading projects from start to finish
Requirements include:
- B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience
- 5+ years hands-on experience in Package/PCB Layout and outing experience, including high-speed design signal integrity practices
- Experience in substrate layout of wire bond and flip-chip packages, preferred
- Knowledge in substrates or board manufacturing process
- Significant background with Cadence Virtuoso and APD (Allegro) or SiP and/or other PCB layout tools
Nice to have:
- Knowledge in Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools
- Familiarity with Skill language (Cadence) and basic parsing abilities (Python/Perl/Shell-scripting)
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