We are seeking a Senior Design Engineer to join our team working on the design of state-of-the-art memory sub-system components used in our industry-leading GPUs and SOCs. In this position, you will be responsible for making architectural trade-offs based on features, performance requirements, and system limitations, coming up with micro-architecture, implementing in RTL, and delivering a fully verified, synthesis/timing clean design.
Your responsibilities will include owning micro-architecture and RTL development of design modules, micro-architecting features to meet performance, power, and area requirements, working with HW architects to define critical features, collaborating with verification teams to verify the correctness of implemented features, interacting with timing, VLSI, and Physical design teams to ensure design meets timing, interface requirements, and is routable, co-operating with FPGA and S/W teams to prototype the design and ensure that S/W is tested, and working on post-silicon verification and debug.
To succeed in this role, you will need a BS/MS or equivalent experience, 4+ years of design experience, experience in micro-architecture and RTL development of complex designs, exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, timing analysis, floor-planning, ECO, bring-up & lab debug, and expertise in Verilog.
A design experience in memory subsystem or network interconnect IP, good debugging and problem-solving skills, scripting knowledge (Python/Perl/shell), and good interpersonal skills and ability & desire to work as a part of a team will also be beneficial.
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