Meta is seeking an ASIC Engineer Intern to join their Infrastructure organization. The role will involve participating in design implementation, physical design, and design power reviews, as well as contributing to optimizing RTL for some of the IPs to achieve best PPA (Power, Performance, Area). The intern will also develop scripts, tools, and methods to enhance PPA and support simulation accelerators and post-Silicon validation.
What you'll do
As an ASIC Engineer Intern, you will be responsible for participating in design implementation, physical design, and design power reviews. You will also contribute to optimizing RTL for some of the IPs to achieve best PPA (Power, Performance, Area).
What you need
To be successful in this role, you will need knowledge of Verilog, VHDL, or HLS, as well as knowledge of Computer Architecture and Logic Design fundamentals.
