We are now looking for a Senior Power Integrity Methodology CAD Engineer to join our team. As an NVIDIAN, you will be immersed in a diverse, supportive environment where everyone is inspired to do their best work.
Role Details:
Responsibilities:
- Develop physical design methodologies for rail analysis and signoff.
- Come up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.
- Craft workflows and tool methodologies for power and noise analysis across multiple projects.
Requirements:
- Master's degree or equivalent experience in Electrical Engineering or related field.
- Minimum 5+ years of experience in EMIR flow methodology development and support.
- Strong understanding of all aspects of EMIR analysis and signoff.
- Familiar with hierarchical design approach and hierarchical signoff.
- Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
- Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff
- Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.
Ways to Stand Out:
- Experience in crafting custom workflows from scratch.
- Adaptability and problem-solving skills: Ability to thrive in a dynamic, fast-paced environment where quick thinking and creative solutions are often required.
- Experience using AI tools to improve capabilities in the power integrity domain, such as automating analysis and improving tool/flow features
You will also be eligible for equity and benefits.
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