We are seeking a Senior Post Silicon Validation Engineer to join our team. As a Senior Post Silicon Validation Engineer, you will be responsible for leading the design, automation, and validation of System Level Tests (SLT) for High Volume Manufacturing (HVM) for complex, high power, high speed System-on-Chip (SoC) designs.
Your primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.
In addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.
You will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.
Finally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.
To be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.
Additionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.
If you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!
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