Opening. We are looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for sub-systems and the full chip.
What you'll do
In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for sub-systems and the full chip. You will participate in the design verification and bring-up of the chip and subsystems by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team.
What you need
- 7+ years of design verification experience with UVM, System Verilog and/or C based testbenches
