Job Posting
ASIC Firmware Engineer, Modeling
Location
San Francisco
Employment Type
Full time
Department
Scaling
Compensation
- $226K – $445K • Offers Equity
The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.
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Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
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Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
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401(k) retirement plan with employer match
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Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
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Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
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13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
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Mental health and wellness support
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Employer-paid basic life and disability coverage
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Annual learning and development stipend to fuel your professional growth
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Daily meals in our offices, and meal delivery credits as eligible
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Relocation support for eligible employees
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Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.
More details about our benefits are available to candidates during the hiring process.
This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.
About the Team
OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
About the Role
We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues.
Responsibilities
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Design and implement drivers for hardware peripherals, including those related to AI chips.
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Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model
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Design and implement low-latency and high throughput embedded SW to manage HW resources.
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Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware.
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Collaborate with vendors to integrate their technologies within our systems.
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Bring up and debug firmware/driver on new platforms.
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Come up with processes and debug issues raised in the field.
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Set up monitoring, integration testing and diagnostics tools.
Qualifications
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5+ years of experience working in embedded SW space.
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Ability to thrive in ambiguity and learn new technologies.
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Strong programming skills in C/C++ and/or Rust.
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Experience developing high throughput, low latency and multi-threaded code.
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Experience working with real time operating systems (RTOS).
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Experience developing hardware drivers and working with hardware
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Experience with HW/SW co-design
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Knowledge of common embedded protocols, e.g. UART, I2C, SPI, etc.
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Knowledge of microprocessor and common ARM architectures (e.g. AMBA) is a plus.
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Knowledge of PCIe, ethernet and other high BW communication protocols is a plus.
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Experience with GPUs or other compute hardware is a plus.
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Experience deploying large compute clusters is a plus.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
