Meta is hiring ASIC Design Verification Engineer within the Infrastructure organisation. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data centre applications.
What you'll do
As a Design Verification Engineer, you will be part of an agile team working with the best in the industry, focused on developing novel ASIC solutions for Meta's data centre applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
What you need
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Track record of 'first-pass success' in ASIC development cycles
- 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
