This role exists to define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification and develop functional tests based on verification test plan.
What you'll do
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification and develop functional tests based on verification test plan.
- Collaborate with cross-functional teams like Design, Model, Emulation, and and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry.
What you need
- Requires a Bachelor’s degree (or foreign degree equivalent) in Computer Science, Electronics Engineering, or related field or a related field and three years of work experience in the job offered or in an engineering related occupation
- Requires three years of experience in the following: System Verilog / UVM, Constraint Random Testbench, IP/SoC (System On Chip) Verification, Debugging design, Functional Coverage, Automation Scripting, Regression management, and Verification IP
